The present invention generally relates to the fabrication of semiconductor substrates from devices, and in particular relates to the use of strained silicon (Si) heterostructure substrates in forming devices such as transistors, for example, for high-performance CMOS integrated circuit products.
As microelectronic systems require faster operating speeds and increased computing power, the need exists for integrated circuits to provide a greater complexity of transistors in a smaller amount of circuit real estate. Such integrated circuits include, for example, microprocessors, ASICs, embedded controllers, and millions of transistors, such as metal oxide silicon semiconductor field-effect transistors (MOSFETs).
Certain microelectronics systems, such as radars, satellites, and cell phones, require low-power, high-speed, and high-density circuits with a high signal-to-noise ratio (i.e., low noise). These low power, high speed, and low noise requirements present a significant design challenge both at the circuit design and at the transistor design level. Microelectronic devices that include both analog and digital circuits are used together to achieve these requirements. Analog devices are used in applications requiring high speed and low noise, whereas digital circuits are used in applications requiring high density and low power.
Microelectronic devices that include both analog and digital circuits on the same substrate typically use traditional Si based MOSFET devices. Analog MOSFET devices, which run on analog signals, typically exhibit noise problems because noise is induced at high frequency when carriers scatter along the Si/SiO2 interface of a traditional MOSFET device. Thus, for high-speed analog devices, field-effect transistors (FETs) are not used; rather, bipolar transistors that do not have conduction along a Si/SiO2 interface are used. Unfortunately, it is difficult and expensive to integrate both bipolar and MOSFET devices on a single substrate.
One way to reduce noise and to achieve devices that are integrated on the same substrate is through changes at the transistor design level by using surface channel devices along with buried channel devices. A conventional Si based buried channel FET device has a channel conduction layer that is buried within a highly doped silicon region. This buried channel device has low noise because the charge carriers in the conduction channel are spatially separated from the Si/SiO2 interface.
While it is possible to build surface channel devices and buried channel devices on the same substrate, the manufacturing process requires complex and extensive process capabilities. For example, use of ion implantation to populate the buried channel requires counterdoping of the layers above the buried channel, and also requires extensive masking steps, adding to the cost and complexity of the overall manufacturing process. Furthermore, the excessive doping required to populate a buried conduction layer within a conventional silicon substrate places fundamental limitations on the performance of such a device.
Further, the use of strained semiconductor devices presents particular problems to the formation of surface channel devices and buried channel devices on the same substrate. For example, U.S. Pat. No. 5,963,817 discloses a method of using local selective oxidation of bulk or strained SiGe for forming buried channel oxide regions involving steps of masking, oxidation (e.g., thermal oxidation), and oxide removal; and U.S. Pat. No. 5,442,205 discloses the formation of surface channel semiconductor heterostructure devices with strained silicon device layers. It has been found, however, that the process of oxidation affects certain strained semiconductors differently. For example, the different layers of a strained semiconductor heterostructure may oxidize or become doped sufficiently differently that device formation procedures are compromised. Moreover, with high thermal budget oxidation, the thin strained semiconductor channels may be destroyed by significant interdiffusion during the high temperature oxidation steps.
There is a need, therefore, for a method of integrating surface channel and buried channel strained silicon devices on the same substrate